The present invention, in some embodiments thereof, relates to a high density memory and, more particularly, but not exclusively, to a high density memory macro for high bandwidth applications.
In light of the growing demands for high-density embedded memories in modern microprocessors and other VLSI System-on-Chip (SoC) designs [1], embedded DRAM (GC-eDRAM) has emerged as an alternative to static random access memory (SRAM) due to its high-density, non-destructive read operation, low leakage power, and two-port operation [2]-[5]. However, this technology requires periodic refresh cycles to reliably retain data, which reduces the memory availability and consumes dynamic refresh power. While GC-eDRAM implementations in mature technology nodes, such as 90 nm and 65 nm, provide long data retention times (DRTs), sub-65 nm technologies suffer from much shorter DRTs due to the reduced parasitic storage capacitances and increased leakage currents [2]-[5].
The conventional and smallest version of a GC-eDRAM is based on the two transistor (2T) bitcell illustrated in FIG. 1. The 2T bitcell is composed of a write port, including a write transistor (NW), a write word-line (WWL), and a write bit-line (WBL); a read port, including a read transistor (NR), a read wordline (RWL), and a read bit-line (RBL); together yielding a bitcell with storage node (SN) capacitance CSN. While the 2T bitcell demonstrated sufficient DRTs in mature technology nodes, it suffers from much lower DRTs in deeply-scaled nodes (below 65 nm) due to reduced parasitic storage capacitances and increased leakage currents.
Additional background art includes:    [1] ITRS, “International Technology Roadmap for Semiconductors—2015 Edition,” 2015. [Online]. Available: http://www(dot)itrs2(dot)net    [2] D. Somasekhar, Y. Ye, P. Aseron, S.-L. Lu, M. M. Khellah, J. Howard, G. Ruhl, T. Karnik, S. Borkar, V. K. De et al., “2 GHz 2 Mb 2T gain cell memory macro with 128 GBytes/sec bandwidth in a 65 nm logic process technology,” IEEE J. Solid-State Circuits, vol. 44, no. 1, pp. 174-185, 2009.    [3] K. C. Chun, P. Jain, T.-H. Kim, and C. H. Kim, “A 667 MHz logic compatible embedded DRAM featuring an asymmetric 2T gain cell for high speed on-die caches,” IEEE J. Solid-State Circuits, vol. 47, no. 2, pp. 547-559, 2012.    [4] Y. S. Park, D. Blaauw, D. Sylvester, and Z. Zhang, “Low-power high throughput LDPC decoder using non-refresh embedded DRAM,” IEEE Journal of Solid-State Circuits, vol. 49, no. 3, pp. 783-794, 2014.    [5] R. Giterman, A. Teman, P. Meinerzhagen, A. Burg, and A. Fish, “4T gain-cell with internal-feedback for ultra-low retention power at scaled CMOS nodes,” in Proc. of IEEE Int. Symp. on Circuits and Systems (ISCAS) 2014. IEEE, 2014, pp. 2177-2180.    [6] P. Gupta, Y. Agarwal, L. Dolecek, N. Dutt, R. K. Gupta, R. Kumar, S. Mitra, A. Nicolau, T. S. Rosing, M. B. Srivastava et al., “Underdesigned and opportunistic computing in presence of hardware variability,” IEEE Transactions on Computer-Aided Design of integrated circuits and systems, vol. 32, no. 1, pp. 8-23, 2013.    [7] A. Sampson, J. Nelson, K. Strauss, and L. Ceze, “Approximate storage in solid-state memories,” ACM Transactions on Computer Systems (TOCS), vol. 32, no. 3, p. 9, 2014.    [8] J. Lucas, M. Alvarez-Mesa, M. Andersch, and B. Juurlink, “Sparkk: Quality-scalable approximate storage in dram,” in The Memory Forum, 2014, pp. 1-9.    [9] S. Ganapathy, A. Teman, R. Giterman, A. Burg, and G. Karakonstantis, “Approximate computing with unreliable dynamic memories,” in New Circuits and Systems Conference (NEWCAS), 2015 IEEE 13th International. IEEE, 2015, pp. 1-4.    [10] N. Edri, P. Meinerzhagen, A. Teman, A. Burg, and A. Fish, “Silicon proven per-cell retention time distribution model of gain-cell based eDRAM,” IEEE Trans. Circuits Syst. I, vol. 63, no. 2, pp. 222-232, February 2016.    [11] U.S. Pat. No. 9,691,445.